1. Technical Field
This patent relates to non-volatile memory devices, and more particularly, to NAND flash memory devices in which one memory block is divided into two sub memory blocks.
2. Discussion of Related Art
A flash memory is a kind of a non-volatile memory in which data can be stored even after power is turned off. The flash memory can be electrically programmed and erased and does not need the refresh function of rewriting data at regular intervals. The term “program” refers to the operation of programming data into the memory cells, and the term “erase” refers to the operation of erasing data from the memory cells.
The flash memory device may be generally classified into NOR flash memory devices and NAND flash memory devices depending on the structure of the cell and operation conditions. In the NOR flash memory device, the source of each memory cell transistor is connected to the ground terminal (VSS) and program and erase for a predetermined address are possible. Accordingly, the NOR flash memory has been mainly used for application fields requiring the high-speed operation. On the other hand, in the NAND flash memory, a plurality of memory cell transistors are connected in series to form a string. One string is connected to the source and the drain of the transistor. The NAND flash memory has been mainly used for high integration data retention fields.
FIG. 1 is a block diagram of memory blocks of a general NAND flash memory device. The NAND flash memory device as shown in FIG. 1 includes memory blocks (i.e., a basic unit of a number of erase operations). In FIG. 1, “BLK<0:n>” indicates the memory block, “BSW<0:n>” indicates a block select switch unit for selecting the memory blocks, and “BSE<0:n>” indicates a block select signal for driving the block select switch unit.
FIG. 2 is a circuit diagram of one memory block consisting of a number of strings.
Referring to FIG. 2, the number of memory cells connected in series between a drain select transistor DST and a source select transistor SST may be 16, 32, 64 or the like considering device and density. Furthermore, a structure in which the two select transistors DST, SST and a plurality of memory cells between the select transistors are connected in series is called a “string”. The drain select transistor DST of the two select transistors is connected to a bit line BL and the source select transistor SST thereof is connected to a common source line CSL.
In general, if the number of memory cells is 32, it is called “32 cell stings”. If the number of memory cells is 64, it is called “64 cell stings”. If the number of memory cells is 16, it is called “16 cell stings”. The number of the memory cells within the memory block may be varied depending on an application. In a product group having the density of 1 G bits or more, 32-cell stings becomes the basis. The flash memory cell basically retains the resistor if it is turned on in the same manner as a general transistor.
FIG. 3a shows a 32-cell sting structure. FIG. 3b shows transistors within the 32-cell sting as resistors. FIG. 3c shows that if a current of 10 μA flows when the bit line BL (drain) is applied with 1V and the gate is applied with a read voltage (Vread=3.5V), a corresponding cell serves as a resistor of 100 Kohm.
As shown in FIG. 3a, even when one selected cell is read in the 32-cell string in which 32 cells are connected in series, current flows through the entire cells constituting the string. In this case, as shown in FIG. 3b, the entire 31 cells other than one read cell operate as resistors. For example, when reading data of cells connected to the word line WL15, 15 cells MC0 to MC14 connected to the word lines WL0 to WL14 become a source-side resistor Rs, and 16 cells MC16 to MC31 connected to the word lines WL16 to WL31 become a drain-side resistor Rd.
In this case, the drain-side resistor Rd functions to drop the bias of the bit line BL, reducing the current level of the linear region. The source-side resistor Rs functions to increase the bias of the common source CSL, reducing the current of the linear region and the saturation region like the back-bias effect. Accordingly, as the cell continues to shrink, the cell current of 32 strings abruptly reduces.
Furthermore, in the string including cells selected during the program operation, a high word line bias (Vpass for by-pass is applied during the program time*31. Therefore, there is a high possibility that a cell state may be changed due to pass disturb in which erase cells are shallowly programmed.
In addition, even in non-selected strings, there is a high possibility that fail may occur due to program disturb in the memory cell MC0 connected to the outermost word line (for example, WL0) during (the program time*31)+the program time.
Furthermore, threshold voltage distributions of a program cell may be increased depending on variation in the threshold voltage of other cells within the same string.